1. Field of the Invention
The invention relates to a plasma display panel (hereinafter, referred to as PDP) and a substrate assembly of a PDP.
2. Description of the Related Art
FIG. 6 is a perspective view showing a structure of a conventional PDP. The PDP has a structure formed by sticking a front-side substrate assembly 1 and a rear-side substrate assembly 2 to each other. The front-side substrate assembly 1 comprises a front-side substrate 1a, which is a glass substrate, and a plurality of display electrodes 3 each composed of a transparent electrode 3a and a metal electrode 3b and placed on the substrate 1a. A dielectric layer 4 covers the display electrodes 3, and further, a protective layer 5, which is a magnesium oxide layer, with a high secondary electron emission coefficient is formed on the dielectric layer 4. In the rear-side substrate assembly 2, a plurality of address electrodes are placed on a rear-side substrate 2a, which is a glass substrate, so that the address electrodes cross at a right angle to the display electrodes. Barrier ribs 7 for defining the light emitting regions (for dividing discharge spaces) are formed between neighboring address electrodes 6 and red-, green-, and blue-emitting phosphor layers 8 are formed on the address electrodes 6 in the regions divided by the barrier ribs 7. A discharge gas, a Ne—Xe gas mixture, is introduced in air-tight discharge spaces divided by the barrier ribs and formed between the front-side substrate assembly 1 and the rear-side substrate assembly 2 stuck to each other. It should be noted that the address electrodes 6 are covered with a dielectric layer (not shown) and the barrier ribs 7 and the phosphor layers 8 are formed on the dielectric layer.
Thus, in such a PDP, address discharge is generated by applying voltage between the address electrodes 6 and the display electrodes 3 also serving as a scan electrode, and reset discharge or sustain discharge for display is generated by applying voltage between a pair of display electrodes 3.
Such PDPs are put to practical use in large flat-screen televisions, and in recent years, development of high-resolution display progresses. As the display becomes higher in resolution, the number of pixels increases. The increase of the number of pixels increases time for addressing, which determines cell's lighting/non-lighting. In order to suppress an increase in the time for addressing (address period), it is necessary to shorten a pulse width of voltage for address discharge (also referred to as address voltage). However, since discharge time-lag (time from application of voltage to occurrence of discharge) varies, discharge can fail to occur when the pulse width of address voltage is too small. In this case, addressed cells do not correctly light in a display period during which lighting of the addressed cells is supposed to be sustained. This causes a problem of deterioration of image quality.
As a means for improving discharge time-lag of such a PDP, an example, in which a magnesium oxide crystal layer is formed on the front-side substrate assembly as an electron-emitting layer, is disclosed in Japanese Patent Application Laid-Open (JP-A) No. 2006-59786.